Datapath Design & ASIC Flow

Overview

This project involved designing and implementing a custom processor datapath using the full ASIC design flow. It spanned RTL development, synthesis, placement and routing (PnR), and physical verification—providing end-to-end exposure to chip implementation.

RTL Design & Synthesis

Starting with a Verilog-based RTL description of a RISC-V-compatible datapath, synthesis was performed using Cadence Genus. Timing constraints and design optimizations were applied to generate a gate-level netlist, ready for backend processing.

Standard Cell Library Integration

To support the physical implementation of the datapath, a custom standard cell library was integrated into the ASIC flow. The stdcells.lef file included detailed layer definitions, via rules, and physical abstracts for essential logic gates and flip-flops. These cells were used during synthesis and layout stages, enabling proper placement, routing, and timing closure in Innovus. Special attention was given to drive strength selection and cell sizing to meet timing and power targets.

Place & Route (PnR)

The netlist was imported into Cadence Innovus, where placement and routing were done targeting a 45nm process node. This phase involved resolving congestion, optimizing timing, and achieving area efficiency.

This project provided a comprehensive journey through the ASIC design pipeline—from RTL design to physical layout and verification. By integrating a custom datapath with a standard cell library and closing timing through synthesis and place-and-route, I gained hands-on experience with real-world chip design constraints and EDA tools like Cadence Genus, Innovus, and Virtuoso. The project not only deepened my understanding of digital design and hardware architecture but also reinforced my passion for building efficient, scalable computing systems at the silicon level.