Krish Patel
University of Illinois Urbana-Champaign
B.S. in Computer Engineering
Carnegie Mellon University
Incoming M.S. in Electrical and Computer Engineering
Hi, I'm Krish
Hardware-Centric Engineer Architecture, Verification, AI
I’m a Computer Engineering graduate passionate about building high-performance systems at the edge of hardware and AI. From OS kernels to RISC-V processors and ML accelerators, I love solving low-level problems with high-level impact.
Education :
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Projects
Out-of-Order RISC-V Processor
Built a 5-stage out-of-order RISC-V processor with reservation stations, a reorder buffer, GShare prediction, and early branch recovery. Included a 4-way set-associative cache for efficient memory access. Verified using VCS, Verilator, and Verdi, and validated with CoreMark and custom testbenches.
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391 Operating System
Developed a UNIX-like operating system from the ground up using embedded C, featuring comprehensive functionalities including paging, keyboard integration, terminal management, and a robust filing system. Enabled scheduling capabilities and support for concurrent usage with up to three terminals running simultaneously. Explore the connected demo
Datapath Design & PnR
Designed and implemented a custom datapath using Cadence tools across the full ASIC flow. Starting with RTL design and synthesis in Genus, the design was placed and routed in Innovus, targeting a 45nm process node. Performed timing optimization, power analysis, and physical verification (DRC/LVS).
Hardware OHLC Generator
Developed a hardware-based OHLC (Open, High, Low, Close) generator in SystemVerilog to process real-time trade data streams. Integrated a parser, control unit, and computation logic to extract symbol-filtered price updates. The design was tested using a custom AXI-based testbench and simulated trade packets, enabling high-throughput financial metric aggregation for HFT applications.
Mortal Kombat on FPGA –
SoC Design & RTL Acceleration
Designed a two-player Mortal Kombat-style fighting game on FPGA using SystemVerilog and Vivado, featuring custom game logic, an animation engine, and real-time HDMI output. Integrated a soft processor to handle inputs and game state, showcasing hardware/software co-design.
Work Experience
May 2024–May 2025
Research Assistant – IBM-IL IIDAI Research Institute
​Optimized tensor compilers by applying NLP-based search space reduction techniques, enhancing cross-platform AI compilation efficiency. Migrated legacy pipelines to a modern TVM framework with less than 2% result variance, and supported research dissemination through abstracts, posters, and technical presentations.
Jan 2025–May 2025
Teaching assistant -
ECE 411 Computer Architecture (UIUC)
Mentored student teams on RISC-V processor design MPs. Guided SystemVerilog debugging using Verdi, and supported pipeline, hazard, and cache logic development. Provided architectural insights and helped refine verification strategies through hands-on reviews.
May 2023–Aug 2024
Intern -
NeoSOFT
developed a deep-learning-based resume parser with 90% accuracy across 1400+ resumes. Built a web scraping bot using BeautifulSoup and Selenium to collect over 1000 job listings into MongoDB, and implemented a Regex-driven skill extraction system that identified 17,000+ unique skills.