Krish Patel
Real-Time Hardware-Accelerated OHLC Aggregator
Overview
In modern financial systems, real-time market data processing is essential for competitive trading. This project demonstrates a hardware-accelerated solution for computing OHLC (Open, High, Low, Close) metrics from NASDAQ and IEX trade data using an FPGA. Traditional software approaches struggle with throughput and latency—this system bypasses those bottlenecks using a fully pipelined, low-latency RTL design.
Architecture & Flow
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The system is composed of multiple hardware modules communicating via AXI-Stream protocols:
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Packet Parsers for IEX DEEP+ and NASDAQ ITCH 5.0
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Decoders to extract symbol, price, timestamp
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OHLC Engine that computes metrics in fixed time windows
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PCAP Injector that simulates real-world traffic in testbenches
The RTL design features a modular pipeline centered around three key components. The Accelerator module serves as the top-level coordinator, managing data flow across submodules using AXI-Stream handshakes to ensure reliable transmission of 64-bit aligned market data. The Decode module (decode.sv) translates raw binary packets from IEX and NASDAQ protocols into structured trade messages, utilizing conditional compilation to support both fixed and variable-length formats. Finally, the Execute module (execute.sv) performs real-time OHLC aggregation, applying symbol-based filtering and time-bucketed updates to compute accurate metrics with sub-microsecond latency.
The simulation and verification environment was built using top_tb.sv and pcap_injector.sv, which together emulate realistic exchange traffic by injecting hex-aligned PCAP payloads into the design. Signal-level behavior was analyzed using Verdi and Synopsys VCS, enabling thorough debugging and validation of the RTL pipeline. The system demonstrated robust performance during simulation, achieving a throughput of over 9.2 million packets per second with deterministic and consistent behavior across test runs.
This project showcases the design of a real-time trading analytics pipeline on FPGA. From binary feed parsing to technical indicator display, it spans the entire data path—from exchange to user interface. The architecture is scalable, modular, and ready for deployment in low-latency HFT environments.